Last updated Sep 17, 2024 Edit Source

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• T1: 1 pair of twisted cable
• UTP: unshielded twisted pair

The purpose of this interface is to provide a simple, inexpensive, and easy-to-implement interconnection between MACs and PHYs

Physical Layer Signaling. Just some abstract primitives and services for communication between PHY and MAC.

• DATA Request: maps the data to the MII signals TXD<3:0>, TX_EN and TX_CLK
• CARRIER: transfers the status of activity on the line. CARRIER_ON = input message, CARRIER_OFF = idle message

PHY Layer Collision Avoidance. An optional feature that can increase bandwidth in high traffic environments meant to tackle limitations of CSMA-CD PLS_DATA with PLCA: Beacon on the line:

Transmit Opportunities (TO) are generated in a round-robin fashion. The node with ID = 0 signals a BEACON on the medium. Reception of a BEACON indicates the start of a new cycle of transmit opportunities. If the node with ID = 0 fails, the network is still operational with the same performance level of a CSMA/CD network without PLCA. Each node is allowed to transmit a single packet during its own transmit opportunity. Individual nodes can be enabled to transmit a number of additional packets, up to the configured limit, within the same transmit opportunity. PLCA relies on the PLS_SIGNAL.indication and PLS_CARRIER.indication primitives to have the MAC delay transmission until a transmit opportunity is available

Essentially

• curID: used to track the node that owns the TO
• to_timer: timer counting down the TO

(Gigabit) Media independent interface. It’s just a name for the standardized interface for connecting different PHYs to the MAC. It functions as a way to allow the MMI to talk to a Manageable Device (MMD). It allows Station Management entities (STA; i.e. could just be some management program or something) to:

• determine PHY capabilities
  • read/write registers on PHY
  • does the PHY support GMII?
• configure the station

Sending data over the MMI uses a specific frame encoding (802.3 22.2.4 onwards)

• PRE: preamble of 32 contiguous 1 bits
• ST: start of frame
• OP: read (10) / write (01)
• PHYAD: address of the PHY
• REGAD: allows accessing 32 individual registers in the PHY. For more registers see MDIO

Registers 13 and 14 provides a way to communicate with a Clause 45 MMD. Access to register 14 will access the register addressed by register 14 if control register is set appropriately.

Management Data Input/Output (Clause 45 ref 45.3 onwards). It provides indirect access for more registers.

Clause 45 MMD’s provide a 16bit address register that is written to during address cycles, or used for indirect access to the register address they contain for data cycles.

• ST: <00> pattern instead of <01>
• OP: importantly, <00> will define the address of the register to be used for data cycles

# PHYuck